1. Field of Invention
The project of TSOC Design of SOC is to develop the Security-Of-Community with the True-System-On-Chip technology. Due to the cost issue, we need the highly integrated and commercialized System-On-Chip SOC design to develop for the Security-Of-Community SOC.
NL-SOC Design has the Clock Chip, Radio Chip, Camera Chip, TV Chip, and Optical Mouse Chip. To save power, the power management has the modes has power down, sleep, dose, normal, turbo. The power sequence has POR, POS, and PDS. The mixed modes design has the mixed Signal, mixed voltage and mixed power. For the power sequence of the mixed mode circuits, it has the mixed voltage POS and PDS. Before, the electronic circuit is system-on-board. In the True-System-On-Chip (TSOC) era, all the components of the board should also implemented on the CMOS chip. However, due to the incompatibility of the component and the CMOS, not all the components and circuits can be integrated on the same CMOS chip. There are still having the crystal of the crystal clock circuit (Xtal Clock), the inductor of the switch mode (SM) power supply, the capacitor of the low drop voltage regulator (LDVR), the capacitor of the de-bounce circuit and the avalanche diode of the true random number generator cannot be integrated in the same CMOS chip.
The 4Less-Xtaless, Capless, Indless, Dioless SOC Design or 4Free-Xtafree, Capfree, Indfree, and Diofree SOC Design is to get rid of all the on-board external components of the SOC design. In other words, the Xtaless Clock chip has no crystal to be the reference. It can generate the accurate reference clocks itself. The Capless LDVR is the low drop voltage regulator having no external on-board capacitor. The Indless SM is the switch-mode power supply having no external on-board inductor. The Dioless TRNG is the true random number generator has no external avalanche diode and it still can generate the true random number. Since all the 4Less-Xtaless, Capless, Indless, Dioless SOC Design or 4Free-Xtafree, Capfree, Indfree, Diofree SOC Design has no external on-board components, all the 4Less-Xtaless, Capless, Indless, Dioless SOC Design or 4Free-Xtafree, Capfree, Indfree, Diofree SOC Design can be system integrated on one single chip to be the true SOC, TSOC. For the 4-less TSOC design, we develop the innovative Self-Compensated SC-PVTANH design methodology. In PVTANH, P is the Process variation; V is the Voltage variation; T is the Temperature variation; A is Aging variation; N is the Noise variation; H is the Humidity variation. There are two type resonators, LC resonator and RC resonator. Both need the Self-Compensated SC-PVTANH to compensate the temperature and humidity variations at the same time. For the SC-PVTANH design methodology, the BGR Bandgap Reference needs to provide the Vbg, Vptat, Vctat,Ibg, Iptat, and Ictat. The bandgap reference is the Vbg & Ibg Bandgap Reference Generator.
In Xtaless Clockchip, the LC resonator is no more to be the free-running architecture. It adopts the constant-gain-boost-Q architecture. In Xtaless Clockchip, the RC resonator is no more to be the fixed triggering architecture that doesn't include the PVT compensation in the feedback loop. It adopts the constant-period-delay-adaptive-triggering architecture to have the PVT compensation in the feedback loop. NL-SOC is Noiseless System On Chip design. P&N Management is the Power & Noise Management of NL-SOC design in the TSOC. It is the 3M design of mixed signal, mixed voltage and mixed power. There are power transient problems of POS (Power On Sequence), POR (Power On Reset) and PDS (Power Down Sequence). For the NL-SOC Noiseless System On Chip design, there is P&N Power and Noise Management. P&N is the abbreviation of Power & Noise. The formalization of P&N Management Problem is the Capless LDVR problem and Indless SM problem, etc.
Capless LDR has the Hybrid Capless-Capfree LDVR (Low Drop Voltage Regulator) and LDIR (Low Drop Current Regulator). The CF-LDVR Capacitor-Free Low Drop Voltage Regulator is for P&N Management.
PHM-SMR is Pulse Hybrid Modulation Adaptive Switch Mode Regulator. The PHM-SBKR is the Pulse Hybrid Modulation Adaptive Switch Mode Buck Regulator. The hybrid mode PHM Controller is one single controller with the unified approach of PWM and PFM. PHM (Adaptive Pulse Hybrid Modulation) is load adaptive to always have the optimum operation. The PHM adopts the sliding control, which is continuous control, no ADC, no DAC. From zero frequency to maximum frequency, PHM has the full range working capability. The PHM Pulse Hybrid Modulation has both the clock period TCK varies and the duty cycle TD varies. PHM is duty-cycle-less. PHM is always at the optimum working condition to have the maximum power efficiency. One Cycle in one clock. PHM can work for both heavy load and light load. PHM is load adaptive. It has no gearshift, and no arbitrator.
Dual Mode SM is the Switch Mode Power Supply having both PWM and PFM controllers. Hybrid Mode APHM-SMR Adaptive Pulse Hybrid Modulation Switch Mode Regulator having only one PHM controller. PHM has both Boost and Buck types SM power supply. For the Buck type APHM-SBKR Adaptive Pulse Hybrid Modulation Switch Mode Buck Regulator, it has both the VCBR (Voltage Controlled Buck Regulator) and ICBR (Current Controlled Buck Regulator).
P&N SOC Design Platform needs the Power Noise Calibration & Simulation & Test. It needs to recognize the P&N Management Problem and make the design evaluation for existed LDO, etc. The laboratory test setup needs to differentiate the ground noise and the oscillation of the LDO
2. Description of Prior Art
Since the SOC of the FSOC (False-System-On-Chip) concept is introduced, the digital circuit and analog circuit even the RF circuit are integrated on one single chip. There are the CameraChip, RadioChip, (Optical) MouseChip and ClockChip, etc. The design methodologies have the mixed-signal design, mixed-mode design, mixed-voltage design, CoSim and CoEm, etc. However, in the lower level of the circuit itself, there is no innovation to make the design to be the TSOC (True-System-On-Chip). Further, in the upper level of system integration doesn't consider the SOC of the Security Of Community, either. The traditional system integration uses the segmental approach. Now, we use the vertical integration approach.
For the Xtaless Clock problem, the traditional xtal clock circuit has one external crystal. The crystal cannot be integrated in the CMOS chip. The high Q resonator needs the high-Q inductor L component such as the crystal has Q=1,000,000. For the on-chip inductor, the inductor has Q=10 only. It is impossible to make the clock chip with the on-chip inductor. Later, there are a lot of efforts trying to use MEM to replace the crystal. However, for the MEM type Xtaless clock chip, not to mention the addition of the process steps, there are the aging of the mechanical stress problem. So, the smarter companies abandons the mechanical MEM approach and adopt no mechanical parts LC resonator type electronic circuit approach. However, they meet the fundamental problems of the low Q of the on-chip inductor problem. Even the interpretation of the papers were not correct, however, it works and proves to be a correct way to approach the Xtaless Clock Chip. But, there are the problems of (1) the inaccuracy of the modeling the inductance, (2) the inaccuracy due to the humidity variation. So far, they fail to recognize the problem that they don't know how to handle these problems.
Since the LC oscillator needs the special RF design techniques. Having only the analog design experience, a lot of companies adopt the traditional RC or IC resonator. However, the traditional RC resonator architecture is for the slow clock being less than 1 MHz. The architecture completely neglects the PVT variations of the digital switching delay circuit in the feedback loop. Today, the company tries to use the same architecture for the 250 MHz to have the less than 4% period variation over PVT variation. They burned a lot of power and barely marginally meet the requirement of the specification. Now the customer asked for 1% variation over 250 MHz, they just don't know how to satisfy the requirement of the customers. Not to mention that they don't know the humidity also playing the important role in the high accurate clock accuracy. They still have far way to go.
The LDR (Low Drop Regulator) has the problem of In-Rush Current, Slew-Rate Voltage, Over-Voltage Protection, etc. The LDVR (Low Drop Voltage Regulator) has the stability problem. The existed capfree LDVR research has (1) NMC: Nested Miller Compensation, GBW=0.4 MHz Phase Margin=61 degrees; (2) DFCFC: Damping Factor Control Frequency Compensation GBW=2.6 MHz Phase Margin=43 degrees; (3) PFC: Positive Feedback Compensation GBW=2.7 MHz Phase Margin=52 degrees; (4) AFFC: Active Feedback Frequency Compensation GBW=4.5 MHz Phase Margin=65 degrees; (5) DLPC: Dual Loop Parallel Compensation GBW=7 MHz Phase Margin=46 degrees; (6) SMC: Single Miller Capacitor Compensation GBW—4.6 MHz Phase Margin=57 degrees; (7) SMFFC: Single Miller Capacitor Feed Forward Compensation GBW=9 MHz Phase Margin=57 degrees. However, all of them still have the similar stability problems to work in the varying loading conditions.
The Switch Cap Power Supply includes the Charge Pump, Voltage Doubler, Voltage Multiplier and Voltage Fractional, etc. The power efficiency is low. So, for the battery efficiency, it must adopt the SM (Switch Mode) power supply. The SM has two kinds, PWM and PFM.
The PWM Pulse Width Modulation has TCK=const and TCK=Tref. The TD varies and Duty Cycle=TD/TCK. The PWM is one cycle having multiple clocks and work for heavy load. The PFM Pulse Frequency Modulation has the TCK varies as TCK=n*Tref and TD=const. PFM is one Cycle with one clock and work for light load. To meet the dynamic varying power requirements of the different modes, it has the dual mode. The Dual Mode is PWM+PFM. It has the dual controllers of PWM and PFM. The PWM controller is for heavy load. The PFM Controller is for light load. It has to add another arbitrator to arbitrate which modes will be used.